Resource Library

IP Talks! at DAC 2023. A presentation by Randy Caplan View>

Videos

View a video of Randy Caplan, CEO Silicon Creations, detailing the Silicon Creations IP portfolio.

SOC Clocking Solutions Require Thought and Planning View>

Articles

by Jeff Galloway and Tom Simon from Silicon Creations

10 Year Anniversary of Solid-State Circuits Society Chapter Poland View>

Articles

This paper presents the origins and evolution if IEEE Solid-State Circuits Society Chapter Poland established in 2013 by a group of microelectronic professional and academics.

Clocking Solutions for IFS 16nm View>

Presentations

Our Fractional-N PLL is production proven with the highest volumes of any mixed signal IP; Collaboration with Intel Foundry Services has helped us port this PLL to Intel 16 with silicon expected soon

One-size-fits-all PLLs for Advanced Samsung Foundry Processes View>

Presentations

Our Fractional-N PLL is production proven with the highest volumes of any mixed signal IP; Collaboration with Samsung Foundry has helped us provide silicon proven FRAC PLLs in 28FDSOI, 10LPP/LPE, 7LPP, and 5LPP with 4LPE silicon expected soon

Product & Company Update from DAC 2022 View>

Videos

Rick Ader, VP Sales gives a product and company update at DAC 2022

Latency Optimized SerDes PMA View>

Flyers | 880kB PDF

An overview of our Ultra-low latency SerDes PMA supporting 10GbE and 25GbE and with in-PMA latency less than 13UI (<1.3ns @ 10.3Gbps). Prints on both sides of one page.

 Maximizing SoC Bandwidth using Dynamic Voltage and Frequency Scaling (Video in Mandarin, PDF in English) View>

Presentations

This paper introduces Silicon Creations fast-Frequency-hopping clock Generator (“FG”) and Delay-to-Digital converter (“DDC”) silicon IP products, along with some typical performance metrics and applications.

One-size-fits-all PLLs for Advanced Samsung Processes View>

Videos

SoC development budgets are growing, and market introduction windows are getting tighter. As a result, companies are spending more and more time and EDA budget on verification. PLLs and clock sources are a vital component in chips – if they do not meet the specification and yield on first silicon the cost of delays and re-spins run to tens of millions of dollars. This paper introduces Silicon Creations (almost) “one-size-fits-all” Fractional-N PLL.

New Products Overview View>

Videos

Introducing two new product lines -- testing now on silicon.

NEW RELEASE
Corporate Social Responsibility View>

Policy and Legal

Silicon Creations has published its CSR report as we formally look beyond the sustainability of our company towards our impact on our communities and our planet.

Silicon Creations PLLs View>

Videos

A brief introduction to our PLL products

Silicon Creations SerDes PMAs View>

Videos

A brief introduction to our SerDes PMA products

Introduction to Silicon Creations View>

Videos

A brief introduction to our company by Andrew Cole.

ISO 9001 Certificate - Poland View>

Policy and Legal

ISO 9001 certification validates that Silicon Creations has met the requirements of the ISO 9001:2015 Quality Management System standard for its Silicon IP Development Procedures and applies to all of Silicon Creations research and development sites worldwide.

ISO 9001 Certificate - U.S. View>

Policy and Legal

ISO 9001 certification validates that Silicon Creations has met the requirements of the ISO 9001:2015 Quality Management System standard for its Silicon IP Development Procedures and applies to all of Silicon Creations research and development sites worldwide.

Brief introductions to our company and product lines provided at "Virtual DAC" 2020 View>

Presentations

Brief introductions to our company and product lines provided at "Virtual DAC" 2020

Flexible Clocking Solutions in Advanced FinFet Processes From 16nm to 5nm View>

Videos

Silicon Creations talks about how a Fractional-N PLL works, why theirs has a DAC inside, and the many different clocking applications solved with their versatile Fractional-N PLL (presented at SemIsrael, June 2020)

Silicon Creations Quality Policy View>

Policy and Legal

In conjunction documenting our procedures for ISO9001 certification, we formalized our quality policy. This is listed here.

Circuit Design and Verification of 7nm Low-Power, Low-Jitter PLLs View>

Presentations

Presented at Mentor U2U conference 2018 in San Jose, CA

Ensuring Silicon Results will Match Circuit Simulation View>

Presentations

Presented at the Mentor 2018 Forums

High Performance PLL Design in TSMC 5nm FinFET Process View>

Presentations

Randy Caplan, Executive VP at Silicon Creations discusses 5nm FinFET design

Pushing the limits of performance for clocking systems using microwatts of system power from 5nm to 180nm View>

Presentations

Andrew Cole, VP at Silicon Creations discusses high performance clocking and SerDes solutions.

5nm Success - Silicon Creations CEO Video Interview at DAC 2019 View>

Videos

Randy Caplan CEO Silicon Creations at DAC 2019 speaks with Graham Bell about the challenge that comes with working on leading-edge technologies and how they overcome them.

SerDes Design Challenges View>

Presentations

Jeff Galloway, VP at Silicon Creations, highlights the challenges, best practices and simulation results involved with a 28nm, 4-lane, 250Mb/s to 12.7Gb/s SERDES design using the AFS Platform at the Mentor U2U Conference in Apr 2016

Developing 7nm IP for Safety Critical Automotive Applications - REUSE 2017 in Santa Clara View>

Presentations

Paper explaining the alphabet soup of automotive safety and how this is assured for IP and using some 7nm IPs to illustrate reliability simulations. Also provides a protocol for pre-qualifying IP reducing the risk of the full chip failing AEC-Q100 qualification due to the IP.

Developing 5nm FinFET PLLs (DAC 2018) View>

Videos

Randy Caplan, VP at Silicon Creations discusses high performance PLL design in 5nm

Silicon Creations 2-page Company and Product Overview View>

Flyers | 799kB PDF file

An overview of our Company and main products. Prints on both sides of one page.

Fractional-N PLLs Overview View>

Flyers | 758kB PDF file

An overview of our Fractional-N PLLs. Prints on both sides of one page.

Multiprotocol SerDes PMA Overview View>

Flyers | 778kB PDF file

An overview of our low power Multiprotocol SerDes PMAs supporting well over 30 protocols. First proven in the Microsemi PolarFire FPGA and ported to 40LP/G, 28HPC+, 12/16FFC, 12LP+ and soon to 6/7FF. Prints on both sides of one page.

LVDS Interface Overview View>

Flyers | 764kB PDF file

Overview of our Bi-directional LVDS I/Os passing 2Gbps and Source-synchronous interfaces for FPD-link, Camera-link, FastLVDS, OpenOLDI, Mini-LVDS and similar protocols. Prints on both sides of one page.

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