Resource Library

Flexible clocking solutions in advanced processes from 180nm to 5nm
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Presentations |

Presented at ICCAD 2019

Circuit Design and Verification of 7nm Low-Power, Low-Jitter PLLs
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Presentations |

Presented at Mentor U2U conference 2018 in San Jose, CA

Ensuring Silicon Results will Match Circuit Simulation
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Presentations |

Presented at the Mentor 2018 Forums

Validating performance of clocking systems using microwatts of system power from 180nm to FinFET
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Presentations |

Presented at ICCAD 2018

Comparing silicon to simulations for a 1.3pJ/bit 25Gbps SerDes Rx in TSMC 28HPC+
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Presentations |

Presented at DAC 2019

High Performance PLL Design in TSMC 5nm FinFET Process
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Presentations |

Randy Caplan, Executive VP at Silicon Creations discusses 5nm FinFET design

Pushing the limits of performance for clocking systems using microwatts of system power from 5nm to 180nm
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Presentations |

Andrew Cole, VP at Silicon Creations discusses high performance clocking and SerDes solutions.

5nm Success - Silicon Creations CEO Video Interview at DAC 2019
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Videos |

Randy Caplan CEO Silicon Creations at DAC 2019 speaks with Graham Bell about the challenge that comes with working on leading-edge technologies and how they overcome them.

Rick Ader Interview at IP-SoC 2019
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Videos |

Time-to-Digital Converter With Sample-and-Hold and Quantization Noise Scrambling Using Harmonics in Ring Oscillators
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Articles |

High-Performance 7nm IP Verification with the AFS Platform
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Articles |

SerDes Design Challenges
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Presentations |

Jeff Galloway, VP at Silicon Creations, highlights the challenges, best practices and simulation results involved with a 28nm, 4-lane, 250Mb/s to 12.7Gb/s SERDES design using the AFS Platform at the Mentor U2U Conference in Apr 2016

Supply Noise Induced Jitter - Don't Let it Kill your Chip
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AnySilicon Presents - CEO Talk with Randy Caplan
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Presentations |

Developing 7nm IP for Safety Critical Automotive Applications - REUSE 2017 in Santa Clara
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Presentations |

Paper explaining the alphabet soup of automotive safety and how this is assured for IP and using some 7nm IPs to illustrate reliability simulations. Also provides a protocol for pre-qualifying IP reducing the risk of the full chip failing AEC-Q100 qualification due to the IP.

SemiWiki - Silicon Creations talks about 7nm IP Verification for AMS Circuits
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Articles |

Developing 5nm FinFET PLLs (DAC 2018)
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Videos |

Randy Caplan, VP at Silicon Creations discusses high performance PLL design in 5nm

Robust Mixed-signal IP in 7nm - 350nm for IoT, Automotive, and beyond (DAC 2017)
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Videos |

Andrew Cole Interview at IP-SoC 2016
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Videos |

Jeff Galloway Interview at IP-SoC 2015
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Videos |

Andrew Cole Interview at IP-SoC 2013
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Videos |

Silicon Creations 2-page Company and Product Overview
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Flyers | 799kB PDF file

An overview of our Company and main products. Prints on both sides of one page.

Fractional-N PLLs Overview
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Flyers | 758kB PDF file

An overview of our Fractional-N PLLs. Prints on both sides of one page.

Multiprotocol SerDes PMA Overview
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Flyers | 778kB PDF file

An overview of our low power Multiprotocol SerDes PMAs supporting well over 30 protocols. First proven in the Microsemi PolarFire FPGA and ported to 40LP, 12FFC and 16FFC. Prints on both sides of one page.

SerDes Interface Overview
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Flyers | 738kB PDF file

This is a brief overview of our targeted SerDes products. The file prints on both sides of one page.

LVDS Interface Overview
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Flyers | 764kB PDF file

Overview of our Bi-directional LVDS I/Os passing 2Gbps and Source-synchronous interfaces for FPD-link, Camera-link, FastLVDS, OpenOLDI, Mini-LVDS and similar protocols. Prints on both sides of one page.

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