Stringent performance requirements for the clocking systems (ultra-low jitter, low power, wide tuning range, and small form factor) mandate careful IP selection, design considerations, and optimization tradeoffs. Silicon Creations engineering team is involved from the beginning to help design SoC clock systems, from IP through distribution to the power delivery network.
A discussion about "the heartbeat of all our gadgets" ...Clocking architecture in Systems on a Chip.
Created by Silicon Creations, AI / NotebookLM Generated
Randy Caplan, CEO at Silicon Creations discusses a milestone for the company.
Chiplets have enabled a powerful new ecosystem of system-on-package with the die-to-die interface being a critical subcomponent of any chiplet design. The data clocking solution can make or break a D2D circuit. Immense performance requirements of the clocking solution (ultra-low jitter, low power, wide tuning range, and small form factor) mandate careful design considerations and optimization tradeoffs. Learn about Silicon Creations’ approach to supporting these challenges.
EP217: The Impact and Unique Business Model of Silicon Creations with Randy Caplan
View a video of Randy Caplan, CEO Silicon Creations, detailing the Silicon Creations IP portfolio.
by Jeff Galloway and Tom Simon from Silicon Creations
This paper presents the origins and evolution if IEEE Solid-State Circuits Society Chapter Poland established in 2013 by a group of microelectronic professional and academics.
Our Fractional-N PLL is production proven with the highest volumes of any mixed signal IP; Collaboration with Intel Foundry Services has helped us port this PLL to Intel 16 with silicon expected soon
Our Fractional-N PLL is production proven with the highest volumes of any mixed signal IP; Collaboration with Samsung Foundry has helped us provide silicon proven FRAC PLLs in 28FDSOI, 10LPP/LPE, 7LPP, and 5LPP with 4LPE silicon expected soon
Rick Ader, VP Sales gives a product and company update at DAC 2022
An overview of our Ultra-low latency SerDes PMA supporting 10GbE and 25GbE and with in-PMA latency less than 13UI (<1.3ns @ 10.3Gbps). Prints on both sides of one page.
Andrew Cole is interviewed by EDACafe
This paper introduces Silicon Creations fast-Frequency-hopping clock Generator (“FG”) and Delay-to-Digital converter (“DDC”) silicon IP products, along with some typical performance metrics and applications.
SoC development budgets are growing, and market introduction windows are getting tighter. As a result, companies are spending more and more time and EDA budget on verification. PLLs and clock sources are a vital component in chips – if they do not meet the specification and yield on first silicon the cost of delays and re-spins run to tens of millions of dollars. This paper introduces Silicon Creations (almost) “one-size-fits-all” Fractional-N PLL.
Silicon Creations has published its CSR report as we formally look beyond the sustainability of our company towards our impact on our communities and our planet.
ISO 9001 certification validates that Silicon Creations has met the requirements of the ISO 9001:2015 Quality Management System standard for its Silicon IP Development Procedures and applies to all of Silicon Creations research and development sites worldwide.
ISO 9001 certification validates that Silicon Creations has met the requirements of the ISO 9001:2015 Quality Management System standard for its Silicon IP Development Procedures and applies to all of Silicon Creations research and development sites worldwide.
Brief introductions to our company and product lines provided at "Virtual DAC" 2020
Silicon Creations talks about how a Fractional-N PLL works, why theirs has a DAC inside, and the many different clocking applications solved with their versatile Fractional-N PLL (presented at SemIsrael, June 2020)
In conjunction documenting our procedures for ISO9001 certification, we formalized our quality policy. This is listed here.
Presented at Mentor U2U conference 2018 in San Jose, CA
Presented at DAC 2019
Randy Caplan, Executive VP at Silicon Creations discusses 5nm FinFET design
Andrew Cole, VP at Silicon Creations discusses high performance clocking and SerDes solutions.
Randy Caplan CEO Silicon Creations at DAC 2019 speaks with Graham Bell about the challenge that comes with working on leading-edge technologies and how they overcome them.
Jeff Galloway, VP at Silicon Creations, highlights the challenges, best practices and simulation results involved with a 28nm, 4-lane, 250Mb/s to 12.7Gb/s SERDES design using the AFS Platform at the Mentor U2U Conference in Apr 2016
Paper explaining the alphabet soup of automotive safety and how this is assured for IP and using some 7nm IPs to illustrate reliability simulations. Also provides a protocol for pre-qualifying IP reducing the risk of the full chip failing AEC-Q100 qualification due to the IP.
Randy Caplan, VP at Silicon Creations discusses high performance PLL design in 5nm
An overview of our Company and main products. Prints on both sides of one page.
An overview of our Fractional-N PLLs. Prints on both sides of one page.
An overview of our low power Multiprotocol SerDes PMAs supporting well over 30 protocols. First proven in the Microsemi PolarFire FPGA and ported to 40LP/G, 28HPC+, 12/16FFC, 12LP+ and 6/7FF. Prints on both sides of one page.
Overview of our Bi-directional LVDS I/Os passing 2Gbps and Source-synchronous interfaces for FPD-link, Camera-link, FastLVDS, OpenOLDI, Mini-LVDS and similar protocols. Prints on both sides of one page.
We offer worldwide sales support through our network of sales partners listed above.
Please let us know how we can help you reach your SoC design goals by contacting
one of our sales representatives, or by contacting us directly.