SoC development budgets are growing, and market introduction windows are getting tighter. As a result, companies are spending more and more time and EDA budget on verification. PLLs and clock sources are a vital component in chips – if they do not meet the specification and yield on first silicon the cost of delays and re-spins run to tens of millions of dollars. This paper introduces Silicon Creations (almost) “one-size-fits-all” Fractional-N PLL.
Silicon Creations has published its first CSR report as we formally look beyond the sustainability of our company towards our impact on our communities and our planet.
ISO 9001 certification validates that Silicon Creations has met the requirements of the ISO 9001:2015 Quality Management System standard for its Silicon IP Development Procedures and applies to all of Silicon Creations research and development sites worldwide.
ISO 9001 certification validates that Silicon Creations has met the requirements of the ISO 9001:2015 Quality Management System standard for its Silicon IP Development Procedures and applies to all of Silicon Creations research and development sites worldwide.
Brief introductions to our company and product lines provided at "Virtual DAC" 2020
Silicon Creations talks about how a Fractional-N PLL works, why theirs has a DAC inside, and the many different clocking applications solved with their versatile Fractional-N PLL (presented at SemIsrael, June 2020)
In conjunction documenting our procedures for ISO9001 certification, we formalized our quality policy. This is listed here.
Presented at Mentor U2U conference 2018 in San Jose, CA
Presented at ICCAD 2018
Presented at DAC 2019
Randy Caplan, Executive VP at Silicon Creations discusses 5nm FinFET design
Andrew Cole, VP at Silicon Creations discusses high performance clocking and SerDes solutions.
Randy Caplan CEO Silicon Creations at DAC 2019 speaks with Graham Bell about the challenge that comes with working on leading-edge technologies and how they overcome them.
Jeff Galloway, VP at Silicon Creations, highlights the challenges, best practices and simulation results involved with a 28nm, 4-lane, 250Mb/s to 12.7Gb/s SERDES design using the AFS Platform at the Mentor U2U Conference in Apr 2016
Paper explaining the alphabet soup of automotive safety and how this is assured for IP and using some 7nm IPs to illustrate reliability simulations. Also provides a protocol for pre-qualifying IP reducing the risk of the full chip failing AEC-Q100 qualification due to the IP.
Randy Caplan, VP at Silicon Creations discusses high performance PLL design in 5nm
An overview of our Company and main products. Prints on both sides of one page.
An overview of our Fractional-N PLLs. Prints on both sides of one page.
An overview of our low power Multiprotocol SerDes PMAs supporting well over 30 protocols. First proven in the Microsemi PolarFire FPGA and ported to 40LP/C, 12/16FFC, 12LP+ and shortly in 6/7FF. Prints on both sides of one page.
Overview of our Bi-directional LVDS I/Os passing 2Gbps and Source-synchronous interfaces for FPD-link, Camera-link, FastLVDS, OpenOLDI, Mini-LVDS and similar protocols. Prints on both sides of one page.
We offer worldwide sales support through our network of sales partners listed above.
Please let us know how we can help you reach your SoC design goals by contacting
one of our sales representatives, or by contacting us directly.