Presented at Mentor U2U conference 2018 in San Jose, CA
Presented at ICCAD 2018
Presented at DAC 2019
Randy Caplan, Executive VP at Silicon Creations discusses 5nm FinFET design
Andrew Cole, VP at Silicon Creations discusses high performance clocking and SerDes solutions.
Randy Caplan CEO Silicon Creations at DAC 2019 speaks with Graham Bell about the challenge that comes with working on leading-edge technologies and how they overcome them.
Jeff Galloway, VP at Silicon Creations, highlights the challenges, best practices and simulation results involved with a 28nm, 4-lane, 250Mb/s to 12.7Gb/s SERDES design using the AFS Platform at the Mentor U2U Conference in Apr 2016
Paper explaining the alphabet soup of automotive safety and how this is assured for IP and using some 7nm IPs to illustrate reliability simulations. Also provides a protocol for pre-qualifying IP reducing the risk of the full chip failing AEC-Q100 qualification due to the IP.
Randy Caplan, VP at Silicon Creations discusses high performance PLL design in 5nm
An overview of our Company and main products. Prints on both sides of one page.
An overview of our Fractional-N PLLs. Prints on both sides of one page.
An overview of our low power Multiprotocol SerDes PMAs supporting well over 30 protocols. First proven in the Microsemi PolarFire FPGA and ported to 40LP, 12FFC and 16FFC. Prints on both sides of one page.
This is a brief overview of our targeted SerDes products. The file prints on both sides of one page.
Overview of our Bi-directional LVDS I/Os passing 2Gbps and Source-synchronous interfaces for FPD-link, Camera-link, FastLVDS, OpenOLDI, Mini-LVDS and similar protocols. Prints on both sides of one page.
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