Title of video: One-size-fits-all PLLs for Advanced Samsung Processes
Presented at Samsung SAFE forum on October 17, 2021
SoC development budgets are growing, and market introduction windows are getting tighter. As a result, companies are spending more and more time and EDA budget on verification. PLLs and clock sources are a vital component in chips – if they do not meet the specification and yield on first silicon the cost of delays and re-spins run to tens of millions of dollars. This paper introduces Silicon Creations (almost) “one-size-fits-all” Fractional-N PLL. It begins by explaining the technical principals behind Fractional-N PLLs in general and then describes what makes this PLL special including an explanation for why there is a DAC inside the PLL. These unique features of the PLL enable us to offer soft IP (delivered as RTL) solutions that can be combined with this PLL to create many useful clocking functions including exact spread spectrum clocks, fully integrated Jitter Cleaners (for PON and Sync-E), micro-degree phase steppers, a solution aligning two clocks anywhere on chip and even a circuit which enables a chip to measure the jitter and duty cycle of clocks without external circuits. In addition to the Fractional-N PLL we also introduce the key features of our Deskew PLLs for DDR low-latency chip-chip interfaces. We offer Fractional and Deskew PLLs which are silicon proven in Samsung’s 28FDSOI, 8LPP and 5LPE, with 4LPP silicon expected soon. This collaboration with Samsung Foundry means we are ready to provide a low-risk solution for almost any clock for your next SoC so you can spend your energy worrying about other parts of your design.
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