Resource Library

Circuit Design and Verification of 7nm Low-Power, Low-Jitter PLLs

Presentations |

Presented at Mentor U2U conference 2018 in San Jose, CA

Ensuring Silicon Results will Match Circuit Simulation

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Presented at the Mentor 2018 Forums

Validating performance of clocking systems using microwatts of system power from 180nm to FinFET

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Presented at ICCAD 2018

Comparing silicon to simulations for a 1.3pJ/bit 25Gbps SerDes Rx in TSMC 28HPC+

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Presented at DAC 2019

High Performance PLL Design in TSMC 5nm FinFET Process

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Randy Caplan, Executive VP at Silicon Creations discusses 5nm FinFET design

Pushing the limits of performance for clocking systems using microwatts of system power from 5nm to 180nm

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Andrew Cole, VP at Silicon Creations discusses high performance clocking and SerDes solutions.

SerDes Design Challenges

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Jeff Galloway, VP at Silicon Creations, highlights the challenges, best practices and simulation results involved with a 28nm, 4-lane, 250Mb/s to 12.7Gb/s SERDES design using the AFS Platform at the Mentor U2U Conference in Apr 2016

Supply Noise Induced Jitter - Don't Let it Kill your Chip

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AnySilicon Presents - CEO Talk with Randy Caplan

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Developing 7nm IP for Safety Critical Automotive Applications - REUSE 2017 in Santa Clara

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Paper explaining the alphabet soup of automotive safety and how this is assured for IP and using some 7nm IPs to illustrate reliability simulations. Also provides a protocol for pre-qualifying IP reducing the risk of the full chip failing AEC-Q100 qualification due to the IP.