Resource Library

Clocking Solutions for IFS 16nm View>

Presentations

Our Fractional-N PLL is production proven with the highest volumes of any mixed signal IP; Collaboration with Intel Foundry Services has helped us port this PLL to Intel 16 with silicon expected soon

One-size-fits-all PLLs for Advanced Samsung Foundry Processes View>

Presentations

Our Fractional-N PLL is production proven with the highest volumes of any mixed signal IP; Collaboration with Samsung Foundry has helped us provide silicon proven FRAC PLLs in 28FDSOI, 10LPP/LPE, 7LPP, and 5LPP with 4LPE silicon expected soon

 Maximizing SoC Bandwidth using Dynamic Voltage and Frequency Scaling (Video in Mandarin, PDF in English) View>

Presentations

This paper introduces Silicon Creations fast-Frequency-hopping clock Generator (“FG”) and Delay-to-Digital converter (“DDC”) silicon IP products, along with some typical performance metrics and applications.

Brief introductions to our company and product lines provided at "Virtual DAC" 2020 View>

Presentations

Brief introductions to our company and product lines provided at "Virtual DAC" 2020

Circuit Design and Verification of 7nm Low-Power, Low-Jitter PLLs View>

Presentations

Presented at Mentor U2U conference 2018 in San Jose, CA

Ensuring Silicon Results will Match Circuit Simulation View>

Presentations

Presented at the Mentor 2018 Forums

High Performance PLL Design in TSMC 5nm FinFET Process View>

Presentations

Randy Caplan, Executive VP at Silicon Creations discusses 5nm FinFET design

Pushing the limits of performance for clocking systems using microwatts of system power from 5nm to 180nm View>

Presentations

Andrew Cole, VP at Silicon Creations discusses high performance clocking and SerDes solutions.

SerDes Design Challenges View>

Presentations

Jeff Galloway, VP at Silicon Creations, highlights the challenges, best practices and simulation results involved with a 28nm, 4-lane, 250Mb/s to 12.7Gb/s SERDES design using the AFS Platform at the Mentor U2U Conference in Apr 2016

Developing 7nm IP for Safety Critical Automotive Applications - REUSE 2017 in Santa Clara View>

Presentations

Paper explaining the alphabet soup of automotive safety and how this is assured for IP and using some 7nm IPs to illustrate reliability simulations. Also provides a protocol for pre-qualifying IP reducing the risk of the full chip failing AEC-Q100 qualification due to the IP.

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