Stringent performance requirements for the clocking systems (ultra-low jitter, low power, wide tuning range, and small form factor) mandate careful IP selection, design considerations, and optimization tradeoffs. Silicon Creations engineering team is involved from the beginning to help design SoC clock systems, from IP through distribution to the power delivery network.
Chiplets have enabled a powerful new ecosystem of system-on-package with the die-to-die interface being a critical subcomponent of any chiplet design. The data clocking solution can make or break a D2D circuit. Immense performance requirements of the clocking solution (ultra-low jitter, low power, wide tuning range, and small form factor) mandate careful design considerations and optimization tradeoffs. Learn about Silicon Creations’ approach to supporting these challenges.
EP217: The Impact and Unique Business Model of Silicon Creations with Randy Caplan
Our Fractional-N PLL is production proven with the highest volumes of any mixed signal IP; Collaboration with Intel Foundry Services has helped us port this PLL to Intel 16 with silicon expected soon
Our Fractional-N PLL is production proven with the highest volumes of any mixed signal IP; Collaboration with Samsung Foundry has helped us provide silicon proven FRAC PLLs in 28FDSOI, 10LPP/LPE, 7LPP, and 5LPP with 4LPE silicon expected soon
This paper introduces Silicon Creations fast-Frequency-hopping clock Generator (“FG”) and Delay-to-Digital converter (“DDC”) silicon IP products, along with some typical performance metrics and applications.
Brief introductions to our company and product lines provided at "Virtual DAC" 2020
Presented at Mentor U2U conference 2018 in San Jose, CA
Presented at DAC 2019
Randy Caplan, Executive VP at Silicon Creations discusses 5nm FinFET design
Andrew Cole, VP at Silicon Creations discusses high performance clocking and SerDes solutions.
Jeff Galloway, VP at Silicon Creations, highlights the challenges, best practices and simulation results involved with a 28nm, 4-lane, 250Mb/s to 12.7Gb/s SERDES design using the AFS Platform at the Mentor U2U Conference in Apr 2016
Paper explaining the alphabet soup of automotive safety and how this is assured for IP and using some 7nm IPs to illustrate reliability simulations. Also provides a protocol for pre-qualifying IP reducing the risk of the full chip failing AEC-Q100 qualification due to the IP.
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Please let us know how we can help you reach your SoC design goals by contacting
one of our sales representatives, or by contacting us directly.