Our SerDes architecture is in production in processes ranging from 12nm to 180nm and at rates from 100Mbps to 32.75Gbps and proven in 12nm. We offer targeted PHYs including JESD204, XAUI, CPRI, SGMII, CPRI, OIF-CEI, V-by-One HS, Infiniband, PCIe1/2/3/4/5 and Serial RapidIO, and a Multiprotocol PMAs covering over 30 protocols from below 250Mbps to 32.75Gbps as well as SerDes designed for custom requirements. We partner with leading controller vendors to provide a complete solution, and can provide a complete PCIe PHY including PIPE PCS.
The examples shown on this page are a small subset of the successful SerDes we have built.
For more information on our SerDes Interfaces please download product overviews of our targeted SerDes PMA and our Multiprotocol SerDes PMA.
Simplified block diagram of Multiprotocol PMA. Features include:
- Supports over 30 protocols including CEI 6G & 11G SR, MR, LR, Ethernet 10GBASE-X/S/K/R, PCIe Gen1/2/3/4, V-by-One HS/US, CPRI, PON, OTN/OTU, 3GSDI, JESD204A/B/C, SATA1-3, XAUI, SGMII
- Programmable (De)Serialization width: 8, 10, 16, 20, 32, or 40 bit
- Tx ring PLL includes fractional multiplication, spread spectrum and Jitter Cleaner function for Sync-E and OTU
- Core-voltage line driver with programmable pre-and post-emphasis
- Out-of-band, electrical idle signaling capability for SAS, SATA, and PCIe
- Ultra-low-Latency optimized PMAs with loop latency from Ser load to Des output ready as low as 23UI (~2.2ns at 10.3Gbps) with 8b Ser/Des word available, and word width down to 8b to match FIFO
- Burst mode CDR with tCDR < 150UI
- Programmable CTLE and adaptive 5-Tap Decision Feedback Equalizer for poor channels
- Non-destructive eye monitor to measure eye opening at data slicer on chip
Excellent jitter performance with a ring PLL. In most cases we can use the on-die Xtal reference which saves an expensive clock chip. Our ring PLL IP can also be used to generate a PCIe2, PCIe3, PCIe4 or PCIe5 compliant reference clock for other PHYs. This eye diagram captured on the output of the PHY we developed for the PolarFire FPGA
with a broad range of protocols validated
shows the excellent signal integrity possible with our low power IP
Delivered including all supplies, ESD and RDL for your bump pitch ... simply drop into layout.
Amongst the more than 25 different PMA IPs our customers have in production are several for JESD204A/B. This JESD204B 4-lane transmitter was developed to occupy one side of a 180nm wirebond packaged ADC. First silicon met the specification and runs up to 7.5Gbps/lane.
A two-chip set receives three DVI signals and packages them to transmit over fiber, regenerating the same DVI stream at the far end
Ring PLLs with wide continuous range and extremely low jitter using only an on-die Xtal reference enable PMAs with low power and low area
Receiver jitter tolerance measured with TSMC 40 LP Multiprotocol PMA shows wide margin to protocols and fast tracking bandwidth.
Easily meeting DisplayPort requirements.
Excellent low jitter is stable over PVT using a ring PLL