SoC development budgets are growing, and market introduction windows are getting tighter. As a result, companies are spending more and more time and EDA budget on verification. PLLs and clock sources are a vital component in chips – if they do not meet the specification and yield on first silicon the cost of delays and re-spins run to tens of millions of dollars. This paper introduces Silicon Creations (almost) “one-size-fits-all” Fractional-N PLL.
Introducing two new product lines -- testing now on silicon.
A brief introduction to our PLL products
A brief introduction to our SerDes PMA products
A brief introduction to our company by Andrew Cole.
Silicon Creations talks about how a Fractional-N PLL works, why theirs has a DAC inside, and the many different clocking applications solved with their versatile Fractional-N PLL (presented at SemIsrael, June 2020)
Randy Caplan CEO Silicon Creations at DAC 2019 speaks with Graham Bell about the challenge that comes with working on leading-edge technologies and how they overcome them.
Randy Caplan, VP at Silicon Creations discusses high performance PLL design in 5nm