Resource Library

One-size-fits-all PLLs for Advanced Samsung Processes
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SoC development budgets are growing, and market introduction windows are getting tighter. As a result, companies are spending more and more time and EDA budget on verification. PLLs and clock sources are a vital component in chips – if they do not meet the specification and yield on first silicon the cost of delays and re-spins run to tens of millions of dollars. This paper introduces Silicon Creations (almost) “one-size-fits-all” Fractional-N PLL.

New Products Overview
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Introducing two new product lines -- testing now on silicon.

Silicon Creations PLLs
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A brief introduction to our PLL products

Silicon Creations SerDes PMAs
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A brief introduction to our SerDes PMA products

Introduction to Silicon Creations
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A brief introduction to our company by Andrew Cole.

Flexible Clocking Solutions in Advanced FinFet Processes From 16nm to 5nm
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Silicon Creations talks about how a Fractional-N PLL works, why theirs has a DAC inside, and the many different clocking applications solved with their versatile Fractional-N PLL (presented at SemIsrael, June 2020)

5nm Success - Silicon Creations CEO Video Interview at DAC 2019
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Randy Caplan CEO Silicon Creations at DAC 2019 speaks with Graham Bell about the challenge that comes with working on leading-edge technologies and how they overcome them.

Rick Ader Interview at IP-SoC 2019
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Developing 5nm FinFET PLLs (DAC 2018)
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Randy Caplan, VP at Silicon Creations discusses high performance PLL design in 5nm

Robust Mixed-signal IP in 7nm - 350nm for IoT, Automotive, and beyond (DAC 2017)
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Andrew Cole Interview at IP-SoC 2016
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Jeff Galloway Interview at IP-SoC 2015
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Andrew Cole Interview at IP-SoC 2013
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