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SerDes Design Challenges

April 26, 2016

Mentor On Demand Seminar “Design and Circuit Verification Challenges of a 250Mbps to 12.7Gbps Multiprotocol SerDes PMA” by Jeff Galloway at Mentor User2User in April, 2016.

This presentation highlights the challenges, best practices and simulation results involved with a 28nm, 4-lane, 250Mb/s to 12.7Gb/s SERDES design using the AFS Platform and includes

Introduction to Silicon Creations and our products
SERDES design and verification challenges
Complexity of circuit verification at advanced processes
Best practices for silicon success using AFS Platform

SerDes Design Challenges

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SerDes Design Challenges

SerDes Design Challenges

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