At the CSIA-ICCAD 2021 Annual Conference & Wuxi IC Industry Innovation and Development Summit (ICCAD 2021) we presented a paper titled "Maximizing SoC Bandwidth using Dynamic Voltage and Frequency Scaling (link to abstract)" with the following sections:
As feature length scaling in advanced CMOS process nodes approaches both economic and physical limits, demand is increasing for improved design methods to support the need for more functionality with fixed power and area budgets. Dynamic Voltage and Frequency Scaling (“DVFS”) is one such method, which can help to ensure every chip is able to operate at the maximum possible speed for the process corner it was fabricated at, regardless of supply voltage level and noise and operating temperature.
Silicon Creations provides modern clocking solutions in the world’s most advanced processes from 3nm to 180nm which enable SoC designers to maximize logic speed and design functionality while minimizing risk and yield loss in high volume production.
This paper introduces Silicon Creations fast-Frequency-hopping clock Generator (“FG”) and Delay-to-Digital converter (“DDC”) silicon IP products, along with some typical performance metrics and applications. Various case studies are described, including implementation of a clock speed control loop to maintain a constant average supply current in the presence of large variations in logic gate activity. Also, initial characterization and background calibration options are described to ensure each individual chip is calibrated to operate at maximum possible speed in any environment.
Silicon Creations’ Frequency Generator and Delay-to-Digital converter are silicon proven in TSMC 5nm FinFET and is currently being ported to other advanced process nodes including TSMC 3nm. We are ready to provide a low-risk solution for almost any clock your next SoC needs so you can spend your energy worrying about other parts of your design.
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