A high-resolution, high-bandwidth, and noise-scrambling, time-to-digital converter (TDC) is presented. Its architecture, which exploits harmonics in ring oscillators, provides a sample-and-hold mechanism in the form of relative phase. This storage mechanism is highly insensitive to noise and allows for oversampling between input events, therefore, can be designed for very high bandwidth. It can achieve lower quantization noise with fewer measurements than noise-shaping TDCs. This paper presents the architecture in detail, an in-depth analysis of noise sensitivity of the time storage mechanism, and the results from a prototype implemented in a 28-nm CMOS process.
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