At Silicon Creations, we have developed a power and area optimized, flexible and programmable PMA (Physical Medium Attachment) architecture that can be reliably ported to different process nodes and scaled across protocol generations as data rates increase.
more information >Silicon Creations stands out as a leader in the semiconductor IP industry, driven by a commitment to innovation, quality, and customer satisfaction. Their cutting-edge PLL and SerDes solutions, coupled with a proven track record of reliability, position them as a trusted partner for semiconductor companies worldwide.
more information >In this article we provide an introduction to DP, talk about the various factors that IC designers will want to consider when integrating the DP functionality into their SOC, and present at a high-level the solutions Silicon Creations provides in this area.
more information >This is the second of two articles highlighting Silicon Creations. In this part, we will explore in more detail how Silicon Creations IP can be used to implement effective solutions that meet technical and business requirements.
more information >This is the first of two articles highlighting Silicon Creations. The second upcoming article will go into more detail on several scenarios showing how Silicon Creations IP is used to solve clocking challenges.
more information >Published in MDPI - November 2022 - Electronics Journals Volume 11 Issue 22
more information >Published in IEEE Solid-State Circuits Magazine - Summer 2022
more information >Published in: IEEE Journal of Solid-State Circuits ( Volume: 56, Issue: 3, March 2021)
more information >Despite their design and verification complexity, SERDES have become an indispensable part of an SoC block. With SERDES IP blocks now available, it’s helped mitigate any cost, risk, and time-to-market escalation.
more information >Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP.
more information >Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production.
more information >SerDes has emerged as the primary solution in chips where there is a need for fast data movement and limited I/O, but this technology is becoming significantly more challenging to work with as speeds continue to rise to offset the massive increase in data.
more information >Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends up on how and where it is used and in part because even the best IP may work better in one system than another—even in chips developed by the same vendor.
more information >
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